1. Field of the Invention
The present invention relates to computer systems, and in particular, to a system and method for loading a program in a reverse order into a memory having one or more defective memory cells.
2. Description of the Prior Art
Memory chips have now reached a high level of technological advancement in which these devices are now capable of storing over a million bits of information in a single semiconductor chip. Since each bit requires at least one transistor and associated circuitry to implement, even the best manufacturing fabrication lines will still turn out memory devices that have numerous bad parts, or memory cells. In the past, memory devices with bad memory cells were typically discarded, thereby resulting in waste and economic loss.
To address this problem, attempts were made to cause a memory device having some defective memory cells to behave as a defect-free memory device. One approach involved the actual repair of defective memory cells or addresses. Actual repair can be accomplished by providing a redundant or substitute memory to store data or program code intended for the defective memory cells or addresses in the memory device. Associated circuitry or software is provided to xe2x80x9clinkxe2x80x9d the defective cells from the regular memory cells to the designated replacement cells in the redundant memory. Laser repair is used to xe2x80x9clinkxe2x80x9d the defective addresses to the designated replacement addresses. Unfortunately, the provision of a redundant memory requires the inclusion of both the redundant memory and additional circuitry, which complicates the design and increases the cost of the memory device. In addition, this approach does not adequately address the situation where either or both the redundant memory and the additional circuitry may be defective.
Yet other attempts have provided memory devices that were both self-testing and self-correcting, such that the efficacy of regular memory cells can be tested while the memory device is in use, and any defective cells can be repaired or corrected by assigning corresponding replacement cells from the redundant memory to replace the defective cells. The location of defective memory cells can be located by any known testing procedure, such as, for example, by alternatively writing xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in each bit location and-then verifying the accuracy of the results. Again, these memory devices experience the same problems described above.
In addition, conventional memory devices that are provided is in the form of an integrated circuit (IC) chip are typically put through an extensive testing procedure during manufacture thereof. Extensive testing of both the logic functions and the memory cells are performed at both the wafer level and at the assembled-package level. Laser repair can also be performed after wafer-level testing. Unfortunately, the testing of on-chip memory is very time-consuming since every memory cell must be tested. In contrast, the testing of logic functions on a chip is less intensive. Therefore, the testing of on-chip memory significantly increases the cost of manufacturing the memory devices.
Furthermore, the conventional method of loading machine code into memory is a xe2x80x9cforwardxe2x80x9d approach that follows the steps illustrated in FIG. 1A. In step 12, the first byte code (e.g. xe2x80x9cEBxe2x80x9d in FIG. 1B), associated with the first machine code address 0000, is loaded into the first memory address 0000 (all addresses are in hexadecimal). In step 14, the next byte code (e.g., xe2x80x9c07xe2x80x9d. in FIG. 1B), associated with the next machine code address 0001, is loaded into the next sequential memory address 0001. In step 18, a determination is made whether the last byte code has been loaded. If yes, then the loading is complete. If no, the processing proceeds to step 14 to load the next byte code. Accordingly, each subsequent byte code is successively loaded into the memory at a subsequent address corresponding to the machine code address, associated with the byte code. Once the last byte code (e.g., xe2x80x9cEExe2x80x9d in FIG. 1B), associated with machine code address 001D, has been loaded into memory address 001D, the loading is completed.
FIG. 1B illustrates an exemplary program code and how it is loaded into memory following the conventional xe2x80x9cforwardxe2x80x9d code loading approach (see arrow that shows the direction of the forward loading). It is noted that the first byte of the machine code is first loaded in the lowest address (i.e., 0000), the next byte is then loaded in a subsequent address, and so on, until the last byte is loaded. in an address equal to the highest machine code address (i.e., 001D), associated with the last byte of the program code. The memory addresses greater than 001D (i.e., 001E to 0028) are not used.
Unfortunately, the xe2x80x9cforwardxe2x80x9d loading scheme has the disadvantage that, once the machine code is loaded into memory, errors that may be due to the existence of one or more defective memory cells can be difficult to correct. For example, the memory shown in FIG. 1B has a defective cell at memory address 0011. Accordingly, instead of a valid byte code at this address location, this location contains invalid information or garbage. In a write-once memory (e.g., a programmable read only memory (PROM), or EPROM), where it is not possible or not convenient to test the memory cells prior to the loading of the machine code for a program, the defective cell at address 0011 will cause the loading of the program code to fail. Moreover, the error is not correctable since the contents of the PROM cannot be over-written. In addition, the contents of the an EPROM cannot be easily erased and rewritten without applying special techniques such as UV exposure.
It is therefore an object of the present invention to provide a computer system and method which overcomes the above-referenced problems.
It is a further object of the present invention to provide a computer system and method in which memory devices having some defective memory cells are made to behave as a defect-free memory device.
It is yet another object of the present invention to provide a computer system and method which can be implemented without adding any additional hardware or memory cells.
It is yet a further object of the present invention to provide a computer system and method which eliminates the need for actual repair or correction of defective memory cells.
It is yet a further object of the present invention to provide a computer system and method which eliminates the need for scanning the memory for defects prior to loading the machine code of the program. Instead, the present invention detects and bypasses defects while loading the program (i.e., xe2x80x9con-the-flyxe2x80x9d detection and correction during loading).
It is yet a further object of the present invention to provide a computer system and method which provides the ability to perform forward address-referencing byte code modification during the loading of the machine code.
It is yet a further object of the present invention to provide a computer system and method which allows for the loading of either the original machine code or an adjusted version of the machine code with modified memory-address referencing byte codes.
It is yet a further object of the present invention to provide a computer system and method in which write-once memory devices having some defective memory cells can be made to behave as a defect-free memory device.
In order to accomplish the objects of the present invention, there is provided a computer system that loads a computer program, in a reverse order, into a memory device having one or more defective memory cells. The program is organized into code modules with each code module including at least one complete instruction or data block. The last code module of the program is loaded first into the last or highest addresses of the address space allocated in the memory for the program. Thereafter, the code module preceding the last loaded code module of the program is loaded into the address preceding the previously-loaded address. The subsequent code modules are loaded into successively lower memory addresses in a reverse fashion until the first code module of the program is loaded into memory.
As each code module, or the codes that make up the code module, are written into a group of memory addresses, a read operation is performed on the memory addresses in that same group, and the read values are compared with the written values. If there is a mis-match at any address, then a defective memory cell exists at that address. The present invention creates and inserts a JUMP instruction into the original program code preceding the defective memory address to bypass any defective memory cell without interrupting the intended operation of the instruction steps that are loaded into the memory. If while loading the JUMP instruction, another memory defect is detected, the present invention creates and inserts another JUMP instruction into the original program code preceding the defective memory address (corresponding to the previous JUMP instruction that failed to load) to bypass any defective memory cell.
A JUMP instruction is also inserted into the memory start address so that a processor is forced to begin execution at the memory address containing the first byte of the first code module. Certain byte codes that include referenced addresses are then modified to correct any address-referencing that may be changed due to the insertion of the JUMP instructions, and then loaded into the appropriate addresses in the memory.